1. Field of the Invention
The present invention relates to a semiconductor memory of multi-bit type which stores and outputs a plurality of bits at the same time, which form a multi-bit data.
2. Description of the Related Art
A digital system having a semiconductor memory such as a DRAM (Dynamic Random-Access Memory) has the following three features to increase the speed of transferring data.
First, the semiconductor memory is a multi-bit type which can store and output the bits forming a multi (.times.2.sup.n)-bit data (n is a natural number), at the same time.
Second, the semiconductor memory stores and outputs data in synchronism with an external clock signal supplied from a CPU (Central Processing Unit). The higher the frequency of the clock signal, the faster the memory (e.g., a SDRAM or a RDRAM) can store and output continuous data. Thus, the memory can serve to increase the speed of transferring data.
Third, the semiconductor memory incorporates a plurality of banks. The banks have identical elements each. The banks can store and output data, independently of one another. These measures taken, the time required to access the first data (known as "latency") is short, thus enhancing the speed of transferring data.
FIG. 1 shows the layout of a conventional semiconductor memory. This memory has all three features mentioned above.
The conventional semiconductor memory comprises a memory chip 10 and four banks 11-0 to 11-3 provided in the chip 10. Each of the banks 11-0 to 11-3 comprises a memory cell array and peripheral circuits such as a cell-array controller, a row address decoder, a column address decoder and a DQ buffer (i.e., a buffer provided in the input/output section of the bank).
The memory chip 10 has input/output region 12. Provided in the data I/O region 12 are a plurality of input/output (I/O) circuits. For example, 16 I/O circuits are provided if the memory chip 10 is designed to store and output 16 bits (i.e., 16-bit data, or 2-byte data) at the same time.
The memory chip 10 also has a data bus 13. The bus 13 extends between one block consisting of the first and second banks 11-0 and 11-1 and the other block consisting of the third and fourth banks 11-2 and 11-3. The data bus 13 is designed to transfer data (e.g., 16-bit data) between each bank and the data I/O region 12.
How the memory chip 10 stores and outputs multi-bit data will be explained.
First, one of the four banks 11-0 to 11-3 is selected. In the bank selected, the memory cell array is accessed on the basis of an address signal. As a result, 2.sup.n -bit (e.g., 16-bit data, or 2-byte data) is output from the bank. The 2.sup.n -bit data is supplied to the data I/O region 12. The I/O region 12 outputs the data. Thus, the 2.sup.n -bit data is output from the memory chip 10.
It is desired that the ratio of the region occupied by the data bus 13 to the all chip area be reduced as much as possible. In other words, the bus 13 needs to be made as thin as possible to decrease the chip area.
However, the greater the number of bits the chip 10 simultaneously store and outputs, the thicker the data bus 13, and hence the larger the region the bus 13 occupies. More specifically, as the number of bits which the memory chip 10 can simultaneously store and output increases (from 16 bits to 32 bits and hence to 64 bits), the area of the memory chip 10 inevitably increases.